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AT91M40800-33AU 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
LQFP-100
描述:
AT91 系列 33 MHz 8 kB SRAM 32位 Thumb 微控制器 - TQFP-100
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AT91M40800-33AU数据手册
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5
1348FS–ATARM–13-Apr-06
AT91M40800
5. Architectural Overview
The AT91M40800 microcontroller integrates an ARM7TDMI with Embedded ICE interface,
memories and peripherals. The architecture consists of two main buses, the Advanced System
Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and
controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-
chip 32-bit memories, the External Bus Interface (EBI) and the AMBA
™
Bridge. The AMBA
Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for
low power consumption.
The AT91M40800 microcontroller implements the ICE port of the ARM7TDMI processor on ded-
icated pins, offering a complete, low cost and easy-to-use debug solution for target debugging.
5.1 Memories
The AT91M40800 microcontroller embeds up to 8K bytes of internal SRAM. The internal mem-
ory is directly connected to the 32-bit data bus and is single-cycle accessible.
The AT91M40800 microcontroller features an External Bus Interface (EBI), which enables con-
nection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit
devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the
early read protocol, enabling faster memory accesses than standard memory interfaces.
5.2 Peripherals
The AT91M40800 microcontrollers integrate several peripherals, which are classified as system
or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can
be programmed with a minimum number of instructions. The peripheral register set is composed
of control, mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and
on- and off-chip memories address space without processor intervention. Most importantly, the
PDC removes the processor interrupt handling overhead, making it possible to transfer up to
64K contiguous bytes without reprogramming the start address, thus increasing the perfor-
mance of the microcontroller, and reducing the power consumption.
5.2.1 System Peripherals
The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8- or
16-bit databus and is programmed through the APB. Each chip select line has its own program-
ming register.
The Power-saving (PS) module implements the Idle mode (ARM7TDMI core clock stopped until
the next interrupt) and enables the user to adapt the power consumption of the microcontroller to
application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal
peripherals and the four external interrupt lines (including the FIQ), to provide an interrupt and/or
fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the
Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to
select specific pins for on-chip peripheral input/output functions, and general-purpose input/out-
put signal pins. The PIO controller can be programmed to detect an interrupt on a signal change
from each line.
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