●逻辑类型Logic Type| 与门 AND Gate \---|--- 电路数Number of Circuits| 1 输入数Number of Inputs| 2 电源电压VccVoltage - Supply| 3V~5.5V 静态电流IqCurrent - Quiescent (Max)| 1uA 输出高,低电平电流Current - Output High, Low| -8mA,8mA 低逻辑电平Logic Level - Low| 0.53V~0.8V 高逻辑电平Logic Level - High| 1.4V~2.0V 传播延迟时间@Vcc,CLMax Propagation Delay @ V, Max CL| 4.2ns @ 4.5V,50pF Description & Applications| 2−Input AND Gate/CMOS Logic Level Shifter;Features High Speed: tPD = 3.5 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 1 uA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 64; Equivalent Gates = 15 Pb−Free Packages are Available 描述与应用| 双输入与门/ CMOS逻辑电平转换器;特性 高速:TPD= VCC= 5.0 V3.5纳秒(典型值) 低功耗:ICC=1 UA TA= 25°C(最大值) TTL兼容的输入:VIL=0.8 V; VIH=2.0 V CMOS兼容输出:VOH> 0.8 VCC VOL<0.1 VCC@负载 掉电保护提供输入和输出 平衡传输延时 引脚和功能兼容与其他标准逻辑系列 芯片的复杂性:场效应管=64;等效门= 15 无铅封装
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2输入与门/CMOS逻辑电平转换器
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