SN74LVC1G00DRLR 数据手册 - TI（德州仪器）

●逻辑类型Logic Type| 与非门 NAND Gate \---|--- 电路数Number of Circuits| 1 输入数Number of Inputs| 2 电源电压VccVoltage - Supply| 1.65V~5.5V 静态电流IqCurrent - Quiescent (Max)| 10µA 输出高，低电平电流Current - Output High, Low| -32mA,32mA 低逻辑电平Logic Level - Low| 0.7 V ~ 0.8 V 高逻辑电平Logic Level - High| 1.7 V ~ 2 V 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL| 4nS @5v,50pF Description & Applications| SINGLE 2-INPUT POSITIVE-NAND GATE； Available in the Texas Instruments NanoStar™ • Ioff Supports Partial-Power-Down Mode Package Operation • Supports 5-V VCC Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • Inputs Accept Voltages to 5.5 V • Max tpd of 3.8 ns at 3.3 V • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) • Low Power Consumption, 10-μA Max ICC – 1000-V Charged-Device Model (C101) • ±24-mA Output Drive at 3.3 V 描述与应用| 单路2输入正与非门; 可用德州仪器NANOSTAR™•IOFF支持部分掉电模式 包装操作 •支持5-V的VCC操作•闭锁性能超过100 mA每 JESD 78，II类 •接受输入电压为5.5 V •最大TPD为3.8 ns在3.3 V •ESD保护超过JESD22 - 2000-V人体模型（A114-A） •低功耗，10μA最大ICC - 1000-V带电器件模型（C101） •±24 mA输出驱动在3.3 V