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HEF4053BT 开发手册 - NXP（恩智浦）
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NXP（恩智浦）
分类:
模拟开关芯片
封装:
SOIC
描述:
NXP HEF4053BT 模拟开关, SPDT, 3 放大器, 60 ohm, 4.5V 至 15.5V, SOIC, 16 引脚
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HEF4053BT数据手册
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AN11051 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Application note Rev. 2 — 15 July 2015 4 of 6
NXP Semiconductors
AN11051
Pin FMEA for HEF4000 family
3. Abbreviations
Table 4. FMEA matrix for pin left open
Pin Class Remarks
Input B undefined operating condition, no damage, increases leakage,
may affect functionality
Output C normal operating condition, no damage, no leakage
V
SS
; V
EE
B undefined operating condition, no damage, increases leakage,
will affect functionality
V
DD
B undefined operating condition, no damage, increases leakage (only for
I/O types), will affect functionality
Table 5. FMEA matrix for pin short-circuits between neighboring pins
Pin Class Remarks
Input to input C if inputs have same voltage levels: no damage, no leakage
B if inputs have different voltage levels: leakage increases, will
affect functionality
Input to output A if input and output have different voltage levels, can cause
high current and can damage device, will affect functionality
C if input and output have same voltage levels, no damage, no
leakage
Input to V
SS
- see Table 3
Input to V
DD
- see Table 2
Output to output C if outputs have same voltage levels, no damage, no leakage
A if outputs have different voltage levels, can cause high
current and can damage device, will affect functionality
Output to input - same effect as ‘input to output’ condition
Output to V
SS
- see Table 3
Output to V
DD
- see Table 2
V
SS
to V
DD
- not applicable, these pins are not neighbors
Table 6. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
FMEA Failure Modes and Effects Analysis
PLL Phase-Locked Loop
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