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MSC8156SVT1000B 开发手册 - Freescale（飞思卡尔）
制造商:
Freescale（飞思卡尔）
分类:
DSP数字信号处理器
封装:
BBGA-783
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MSC8156SVT1000B数据手册
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MSC8156 Product Brief, Rev. 3
Features
Freescale Semiconductor6
– Writing policy programmable per memory segment as either write-back or write-through
– 0.25 Kbytes Write-back Buffer (WBB)
– Six 64bit entry WTB
– Line pre-fetch capability
– Software pre-fetch, synchronize, and flush support by core instructions
— Unified L2 Cache/M2 Memory:
– 512 Kbyte
– 8 ways with 1024 indexes and a 64 byte line
– Physically addressed
– Dynamically configured as a DMA accessible M2 Memory
– Maximum user flexibility for real time support through address partitioning of the cache
– Support various write policies and methods to reduce cache inclusiveness
– Multi-channel, two dimensional software pre-fetch support
– Software coherency support with seamless transition from L1 cache coherency operation.
— Memory management unit (MMU):
– Highly flexible memory mapping capability
– Provides virtual to physical address translation
– Provides task protection
– Supports multi-tasking
– Supports precise interrupts. Enabling to have an open RTOS.
— Debug and Profiling Unit (DPU) block:
– Supports the debugging and profiling of the platform in cooperation with the OCE Block
– Supports various breakpoint and event counting options
– Supports real-time tracing to the main memory with the Trace Write Buffer (TWB)
— Extended programmable interrupt controller (EPIC)
– 256 interrupts
– 32 priority levels with NMI support
— Two general-purpose 32-bit timers
— Low-power design with the following modes of operation:
– Wait processing state for peripheral operation
– Stop processing state
– Power down processing state
— ECC/EDC support.
• Chip-level arbitration and switching system (CLASS)
— A full fabric that arbitrates between the DSP cores and other CLASS masters to the core M2
memory, shared M3 memory, DDR SDRAM controllers, MAPLE-B, and the device
configuration control and status registers (CCSRs).
— High bandwidth.
— Non-blocking allows parallel accesses from multiple initiators to multiple targets.
— Fully pipelined.
— Low latency.
— Per target arbitration highly optimized to the target characteristics using prioritized round-robin
arbitration.
— Reduces data flow bottlenecks and enables high-bandwidth internal data transfers.
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