Datasheet 搜索 > FPGA芯片 > Altera(阿尔特拉) > 5AGXFB3H4F35I3N 数据手册 > 5AGXFB3H4F35I3N 数据手册 1/41 页


¥ 7600.736
5AGXFB3H4F35I3N 数据手册 - Altera(阿尔特拉)
制造商:
Altera(阿尔特拉)
分类:
FPGA芯片
封装:
FBGA-1152
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P35Hot
典型应用电路图在P6P8P10P12P14
型号编码规则在P6P8P10P12P14
封装信息在P2
导航目录
5AGXFB3H4F35I3N数据手册
Page:
of 41 Go
若手册格式错乱,请下载阅览PDF原文件

Arria V Device Overview
2015.01.23
AV-51001
Subscribe
Send Feedback
The Arria
®
V device family consists of the most comprehensive offerings of mid-range FPGAs ranging
from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-
range FPGA bandwidth 12.5 Gbps transceivers.
The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging,
switching, and packet processing applications, high-definition video processing and image manipulation,
and intensive digital signal processing (DSP) applications.
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Key Advantages of Arria V Devices
Table 1: Key Advantages of the Arria V Device Family
Advantage Supporting Feature
Lowest static power in its
class
• Built on TSMC's 28 nm process technology and includes an abundance of
hard intellectual property (IP) blocks
• Power-optimized MultiTrack routing and core architecture
• Up to 50% lower power consumption than the previous generation
device
• Lowest power transceivers of any midrange family
Improved logic integration
and differentiation capabil‐
ities
• 8-input adaptive logic module (ALM)
• Up to 38.38 megabits (Mb) of embedded memory
• Variable-precision digital signal processing (DSP) blocks
Increased bandwidth
capacity
• Serial data rates up to 12.5 Gbps
• Hard memory controllers
Hard processor system
(HPS) with integrated
ARM
®
Cortex
™
-A9
MPCore processor
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor,
hard IP, and an FPGA in a single Arria V system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency
between the processor and the FPGA fabric
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册,每天更新 5,000 多个 PDF 文件