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5CGXBC9E6F31C7 数据手册 - Altera（阿尔特拉）
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Altera（阿尔特拉）
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5CGXBC9E6F31C7数据手册
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Advantage Supporting Feature
Lowest system cost
• Requires only two core voltages to operate
• Available in low-cost wirebond packaging
• Includes innovative features such as Configuration via Protocol (CvP)
and partial reconfiguration
Summary of Cyclone V Features
Table 2: Summary of Features for Cyclone V Devices
Feature Description
Technology • TSMC's 28-nm low-power (28LP) process technology
• 1.1 V core voltage
Packaging • Wirebond low-halogen packages
• Multiple device densities with compatible package footprints for seamless
migration between different device densities
• RoHS-compliant and leaded
(1)
options
High-performance
FPGA fabric
Enhanced 8-input ALM with four registers
Internal memory
blocks
• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can
use up to 25% of the ALMs as MLAB memory
Embedded Hard IP
blocks
Variable-precision
DSP
• Native support for up to three signal processing precision
levels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in
the same variable-precision DSP block
• 64-bit accumulator and cascade
• Embedded internal coefficient memory
• Preadder/subtractor for improved efficiency
Memory controller DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support
Embedded
transceiver I/O
PCI Express
®
(PCIe
®
) Gen2 and Gen1 (x1, x2, or x4) hard IP
with multifunction support, endpoint, and root port
Clock networks • Up to 550 MHz global clock network
• Global, quadrant, and peripheral clock networks
• Clock networks that are not used can be powered down to reduce dynamic power
(1)
Contact Altera for availability.
2
Summary of Cyclone V Features
CV-51001
2016.06.10
Altera Corporation
Cyclone V Device Overview
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