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74HC00PW,112 数据手册 - NXP（恩智浦）
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NXP（恩智浦）
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逻辑芯片
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TSSOP-14
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74HC00PW,112数据手册
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74HC_HCT00 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7 — 25 November 2015 7 of 15
NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Test data is given in Table 9.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= load capacitance including jig and probe capacitance.
Fig 7. Test circuit for measuring switching times
DDK
W
:
W
:
W
U
W
U
W
I
9
0
9
,
QHJDWLYH
SXOVH
*1'
9
,
SRVLWLYH
SXOVH
*1'
9
0
9
0
9
0
W
I
9
&&
'87
5
7
9
,
9
2
&
/
*
Table 9. Test data
Type Input Load Test
V
I
t
r
, t
f
C
L
74HC00 V
CC
6.0 ns 15 pF, 50 pF t
PLH
, t
PHL
74HCT00 3.0 V 6.0 ns 15 pF, 50 pF t
PLH
, t
PHL
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