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74HC138PW 数据手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
多工器
封装:
TSSOP-16
描述:
74HC 系列解码器/多路复用器，NXP 74HC 系列 CMOS 逻辑 IC 的解码器、多路复用器、多路信号分离器和模拟开关系列。 74HC 系列使用硅门 CMOS 技术，实现与 LSTTL 系列类似的工作速度，但标准 CMOS 集成电路功耗降低。 74HC 系列
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74HC138PW数据手册
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1. General description
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2)
to eight mutually exclusive outputs (Y
0 to Y7). The device features three enable inputs
(E
1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines)
decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an eight output
demultiplexer by using one of the active LOW enable inputs as the data input and the
remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC138: CMOS level
For 74HCT138: TTL level
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 5 — 26 January 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC138N 40 Cto+125C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT138N
74HC138D 40 Cto+125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74 HCT138D
74HC138DB 40 Cto+125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT138DB
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