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AD5062BRJZ-2500RL7 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
DA转换器
封装:
SOT-23-8
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16 位，单通道，Analog Devices### 数字到模拟转换器 - Analog Devices
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AD5062BRJZ-2500RL7数据手册
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AD5062
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5062
TOP VIEW
(Not to Scale)
V
OUT
SYNC
18
AGND
SCLK
27
DIN
DACGND
36
04766-003
V
REF
45
V
DD
Figure 3.
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2
V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and V
DD
should be decoupled to GND.
3 V
REF
Reference Voltage Input.
4 V
OUT
Analog Output Voltage from DAC.
5 AGND Ground Reference Point for Analog Circuitry.
6 DACGND Ground Input to the DAC.
7
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC
is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
8 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
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