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AD5162BRMZ100-RL7
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AD5162BRMZ100-RL7数据手册
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AD5162
Rev. C | Page 5 of 20
TIMING CHARACTERISTICS: ALL VERSIONS
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
SPI INTERFACE TIMING CHARACTERISTICS
1
Clock Frequency f
CLK
25 MHz
Input Clock Pulse Width t
CH
, t
CL
Clock level high or low 20 ns
Data Setup Time t
DS
5 ns
Data Hold Time t
DH
5 ns
CS
t
CSS
Setup Time 15 ns
CS
t
CSW
High Pulse Width 40 ns
CLK Fall to
CS
t
CSH0
Fall Hold Time 0 ns
CLK Fall to
CS
t
CSH1
Rise Hold Time 0 ns
CS
t
CS1
Rise to Clock Rise Setup 10 ns
1
See the timing diagrams for the locations of measured values (that is, see Figure 42 and Figure 43).

AD5162BRMZ100-RL7 数据手册

ADI(亚德诺)
20 页 / 0.8 MByte
ADI(亚德诺)
18 页 / 0.53 MByte
ADI(亚德诺)
7 页 / 0.71 MByte
ADI(亚德诺)
6 页 / 0.1 MByte

AD5162BRMZ100 数据手册

ADI(亚德诺)
ANALOG DEVICES  AD5162BRMZ100  易失性数字电位器, 100 kohm, 双, 3线, 串行, 线性, ± 20%, 2.7 V
ADI(亚德诺)
双通道, 256位, SPI数字电位计 Dual, 256-Position, SPI Digital Potentiometer
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