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器件3D模型￥ 110.028
AD8113JST 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
模拟开关芯片
封装:
LQFP
描述:
音频/视频60 MHz的16× 16 ，G = + 2交叉点开关 Audio/Video 60 MHz 16 X 16, G = + 2 Crosspoint Switch
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AD8113JST数据手册
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REV. A
AD8113
–7–
PIN FUNCTION DESCRIPTIONS
Mnemonic Pin Numbers Pin Description
INxx 58, 60, 62, 64, 66, 68, 70, 72, Analog Inputs; xx = Channel Numbers 00 through 15.
4, 6, 8, 10, 12, 14, 16, 18
DATA IN 96 Serial Data Input, TTL Compatible.
CLK 97 Clock, TTL Compatible. Falling Edge Triggered.
DATA OUT 98 Serial Data Out, TTL Compatible.
UPDATE 95 Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.
Data latched when High.
RESET 100 Disable Outputs, Active Low.
CE 99 Chip Enable, Enable Low. Must be low to clock in and latch data.
SER/PAR 94 Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected.
OUTyy 53, 51, 49, 47, 45, 43, 41, 39, Analog Outputs yy = Channel Numbers 00 Through 15.
37, 35, 33, 31, 29, 27, 25, 23
AGND 3, 5, 7, 9, 11, 13, 15, 17, 19, 57, Analog Ground for Inputs and Switch Matrix. Must be connected.
59, 61, 63, 65, 67, 69, 71, 73
DV
CC
1, 75 5 V for Digital Circuitry.
DGND 2, 74 Ground for Digital Circuitry.
AV
EE
20, 56 –5 V for Inputs and Switch Matrix.
AV
CC
21, 55 5 V for Inputs and Switch Matrix.
AV
CC
xx/yy 54, 50, 46, 42, 38, 34, 30, 26, 22 5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
AV
EE
xx/yy 52, 48, 44, 40, 36, 32, 28, 24 –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
A0 84 Parallel Data Input, TTL Compatible (Output Select LSB).
A1 83 Parallel Data Input, TTL Compatible (Output Select).
A2 82 Parallel Data Input, TTL Compatible (Output Select).
A3 81 Parallel Data Input, TTL Compatible (Output Select MSB).
D0 80 Parallel Data Input, TTL Compatible (Input Select LSB).
D1 79 Parallel Data Input, TTL Compatible (Input Select).
D2 78 Parallel Data Input, TTL Compatible (Input Select).
D3 77 Parallel Data Input, TTL Compatible (Input Select MSB).
D4 76 Parallel Data Input, TTL Compatible (Output Enable).
NC 85–93 No Connect.
Figure 5. I/O Schematics
ESD
ESD
INPUT
V
CC
AV
EE
a. Analog Input
ESD
ESD
RESET
V
CC
20k⍀
DGND
c. Reset Input
ESD
ESD
OUTPUT
V
CC
AV
EE
b. Analog Output
ESD
ESD
INPUT
V
CC
DGND
d. Logic Input
ESD
ESD
OUTPUT
V
CC
2k⍀
DGND
e. Logic Output
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