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器件3D模型￥ 45.063
AD8221TRMZ-EP 数据手册 - ADI（亚德诺）
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ADI（亚德诺）
分类:
运算放大器
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TSSOP-8
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仪表放大器 Precision Instrumentation Amplifier
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AD8221TRMZ-EP数据手册
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SM320C6201-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SGUS041A -- MAY 2003 -- REVISED JANUARY 2004
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443
D Controlled Baseline
-- One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
-- 4 0 °C to 105°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
†
D High-Performance Fixed-Point Digital
Signal Processor (DSP) SM320C6201
-- 5-ns Instruction Cycle Time
-- 200-MHz Clock Rate
-- Eight 32-Bit Instructions/Cycle
-- 1600 MIPS
D VelociTI™ Advanced Very Long Instruction
Word (VLIW) TMS320C62x™ DSP CPU Core
-- Eight Independent Functional Units:
-- Six Arithmetic Logic Units (ALUs)
(32-/40-Bit)
-- Two 16-Bit Multipliers (32-Bit Results)
-- Load-Store Architecture With 32 32-Bit
General-Purpose Registers
-- Instruction Packing Reduces Code Size
-- All Instructions Conditional
D Instruction Set Features
-- Byte-Addressable (8-, 16-, 32-Bit Data)
-- 32-Bit Address Range
-- 8-Bit Overflow Protection
-- Saturation
-- Bit-Field Extract, Set, Clear
-- Bit-Counting
-- Normalization
D 1M-Bit On-Chip SRAM
-- 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
-- 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency
D 32-Bit External Memory Interface (EMIF)
-- Glueless Interface to Asynchronous
Memories: SRAM and EPROM
-- Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
D Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
D 16-Bit Host -Port Interface (HPI)
-- Access to Entire Memory Map
D Two Multichannel Buffered Serial Ports
(McBSPs)
-- Direct Interface to T1/E1, MVIP, SCSA
Framers
-- ST-Bus-Switching Compatible
-- Up to 256 Channels Each
-- AC97-Compatible
-- Serial Peripheral Interface (SPI)
Compatible (Motorola™)
D Two 32-Bit General-Purpose Timers
D Flexible Phase-Locked Loop (PLL) Clock
Generator
D IEEE-1149.1 (JTAG
‡
) Boundary-Scan
Compatible
D 352-Pin BGA Package (GJC Suffix)
D CMOS Technology
-- 0.18-μm/5-Level Metal Process
D 3.3-V I/Os, 1.8-V Internal
Please be aware that an important notice concerning availab ility, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI and TMS320C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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