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ADF4113BRUZ
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RF PLL Frequency Synthesizers
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (V
P
) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
GENERAL DESCRIPTION
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downcon-
version sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
N = BP + A
FUNCTION
LATCH
PRESCALER
P/P +1
13-BIT
B COUNTER
6-BIT
A COUNTER
14-BIT
R COUNTER
24-BIT
INPUT REGISTER
R COUNTER
LATCH
A, B COUNTER
LATCH
PHASE
FREQUENCY
DETECTOR
AV
DD
SD
OUT
19
13
14
22
SD
OUT
FROM
FUNCTION
LATCH
DGNDAGNDCE
RF
IN
A
RF
IN
B
LE
DATA
CLK
REF
IN
CPGND
V
P
DV
DD
AV
DD
LOCK
DETECT
ADF4110/ADF4111
ADF4112/ADF4113
6
LOAD
LOAD
REFERENCE
CHARGE
PUMP
M3 M2 M1
HIGH Z
MUX
MUXOUT
CP
R
SET
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
CURRENT
SETTING 1
03496-0-001
Figure 1. Functional Block Diagram

ADF4113BRUZ 数据手册

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