Datasheet 搜索 > 开发套件与开发板 > ADI（亚德诺） > AD-FMCOMMS3-EBZ 数据手册 > AD-FMCOMMS3-EBZ 数据手册 6/36 页
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AD-FMCOMMS3-EBZ 数据手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
开发套件与开发板
封装:
-
描述:
ANALOG DEVICES AD-FMCOMMS3-EBZ 评估板, AD9361 射频 AGILE 收发器
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P7P16Hot
原理图在P1
封装尺寸在P36
型号编码规则在P36
封装信息在P36
焊接温度在P15
功能描述在P1P7P16
技术参数、封装参数在P1P3P5P15
应用领域在P1
电气规格在P3P20
导航目录
AD-FMCOMMS3-EBZ数据手册
Page:
of 36 Go
若手册格式错乱，请下载阅览PDF原文件
AD9361 Data Sheet
Rev. D | Page 6 of 36
Parameter
1
Symbol Min Typ Max Unit
Test Conditions/
Comments
Logic Outputs
Output Voltage
High 1375 mV
Low 1025 mV
Output Differential Voltage 150 mV Programmable in 75 mV
steps
Output Offset Voltage 1200 mV
GENERAL-PURPOSE OUTPUTS
Output Voltage
High VDD_GPO × 0.8 V
Low VDD_GPO × 0.2 V
Output Current 10 mA
SPI TIMING VDD_INTERFACE = 1.8 V
SPI_CLK
Period t
CP
20 ns
Pulse Width t
MP
9 ns
SPI_ENB Setup to First SPI_CLK
Rising Edge
t
SC
1 ns
Last SPI_CLK Falling Edge to
SPI_ENB Hold
t
HC
0 ns
SPI_DI
Data Input Setup to SPI_CLK t
S
2 ns
Data Input Hold to SPI_CLK t
H
1 ns
SPI_CLK Rising Edge to Output
Data Delay
4-Wire Mode t
CO
3 8 ns
3-Wire Mode t
CO
3 8 ns
Bus Turnaround Time, Read t
HZM
t
H
t
CO (max)
ns After BBP drives the last
address bit
Bus Turnaround Time, Read t
HZS
0 t
CO (max)
ns After AD9361 drives the
last data bit
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK Clock Period t
CP
16.276 ns 61.44 MHz
DATA_CLK and FB_CLK Pulse
Width
t
MP
45% of t
CP
55% of t
CP
ns
TX Data TX_FRAME, P0_D, and
P1_D
Setup to FB_CLK t
STX
1 ns
Hold to FB_CLK t
HTX
0 ns
DATA_CLK to Data Bus Output
Delay
t
DDRX
0 1.5 ns
DATA_CLK to RX_FRAME Delay t
DDDV
0 1.0 ns
Pulse Width
ENABLE t
ENPW
t
CP
ns
TXNRX t
TXNRXPW
t
CP
ns FDD independent ENSM
mode
TXNRX Setup to ENABLE t
TXNRXSU
0 ns TDD ENSM mode
Bus Turnaround Time
Before RX t
RPRE
2 × t
CP
ns TDD mode
After RX t
RPST
2 × t
CP
ns TDD mode
Capacitive Load 3 pF
Capacitive Input 3 pF
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