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ADP5300ACPZ-1-R7
器件3D模型
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ADP5300ACPZ-1-R7数据手册
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Data Sheet ADP5300
Rev. A | Page 7 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1EN
2STOP
3SYNC/MODE
4VID
5FB
10 PVIN
9SW
8PGND
7AGND
6VOUTOK
TOP VIEW
(Not to Scale)
ADP5300
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO A
LARGE EXTERNAL COPPER GROUND PLANE
UNDERNEATH THE IC FOR THERMAL DISSIPATION.
13366-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN Enable Input for the Regulator. Set to logic low to disable the regulator.
2 STOP
Stop Switching Input Signal. When this pin is logic high, the regulator stops the regulator switching. When this
pin is logic low, the regulator resumes the regulator switching.
3 SYNC/MODE
Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock,
connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz.
PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM mode.
When this pin is logic low, the regulator operates in hysteresis mode.
4 VID
Voltage Configuration Pin. Connect an external resistor (R
VID
) from this pin to ground to configure the output
voltage of the regulator (see Table 5).
5 FB Feedback Sensing Input for the Regulator.
6 VOUTOK Output Power-Good Signal. This open-drain output is the power-good signal for the output voltage.
7 AGND Analog Ground.
8 PGND Power Ground.
9 SW Switching Node Output for the Regulator.
10 PVIN Power Input for the Regulator.
EPAD
Exposed Pad. The exposed pad must be soldered to a large external copper ground plane underneath the IC for
thermal dissipation.

ADP5300ACPZ-1-R7 数据手册

ADI(亚德诺)
21 页 / 0.71 MByte
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ADP5300ACPZ1 数据手册

ADI(亚德诺)
直流-直流开关降压稳压器, 可调, 2.15V-6.5V输入, 0.8V-5V输出, 500mA输出, LFCSP-10
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