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ATMEGA325P-20MU 数据手册 - ATMEL（爱特美尔）
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ATMEL（爱特美尔）
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微控制器
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VFQFN-64
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ATMEGA325P-20MU数据手册
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3
8023FS–AVR–07/09
ATmega325P/3250P
Figure 1-2. Pinout ATmega325P
Note: The large center pad underneath the QFN/MLF packages is made of metal and internally con-
nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.
1.1 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2. Overview
The ATmega325P/3250P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega325P/3250P achieves throughputs approaching 1 MIPS
per MHz allowing the system designer to optimize power consumption versus processing speed.
PC0
VCC
GND
PF0 (ADC0)
PF7 (ADC7/TDI)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
AREF
GND
AVCC
17
61
60
18
59
20
58
19
21
57
22
56
23
55
24
54
25
53
26
52
27
51
29
28
50
49
32
31
30
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
DNC
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC2A/PCINT15) PB7
(T1) PG3
(OC1B/PCINT14) PB6
(T0) PG4
(OC1A/PCINT13) PB5
PC1
PG0
PD7
PC2
PC3
PC4
PC5
PC6
PC7
PA 7
PG2
PA 6
PA 5
PA 4
PA 3
PA 0
PA 1
PA 2
PG1
PD6
PD5
PD4
PD3
PD2
(INT0) PD1
(ICP1) PD0
(TOSC1) XTAL1
(TOSC2) XTAL2
RESET/PG5
GND
VCC
INDEX CORNER
(SS/PCINT8) PB0
2
3
1
4
5
6
7
8
9
10
11
12
13
14
16
15
64
63
62
47
46
48
45
44
43
42
41
40
39
38
37
36
35
33
34
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