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ATTINY24A-SSN 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
8位微控制器
封装:
SOIC-14
描述:
8位 MCU微控制单元, AVR ATtiny Family ATtiny24 Series Microcontrollers, 20 MHz, 2 KB, 128 Byte, 14 引脚
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引脚图在P8P9P61P294Hot
典型应用电路图在P128
原理图在P10P13P59P74P76P77P78P91P93P95P97P99
型号编码规则在P276P277P278P294
封装信息在P279P280P281P283P284P285P286P287P288
功能描述在P123
应用领域在P38
电气规格在P156
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ATTINY24A-SSN数据手册
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ATtiny24A/44A/84A
2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 61
10.1.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
10.1.3 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b10) as an intermediate step.
Table 10-1 summarizes the control signals for the pin value.
10.1.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 10-2 on page 60, the PINxn Register bit and the preced-
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
Table 10-1. Port Pin Configurations
DDxn PORTxn
PUD
(in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
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