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ATTINY85V-10SU 数据手册 - ATMEL（爱特美尔）
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ATMEL（爱特美尔）
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微控制器
封装:
SOIC-8
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ATMEL ATTINY85V-10SU 微控制器, 8位, 低功率高性能, ATtiny, 10 MHz, 8 KB, 512 Byte, 8 引脚, SOIC
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ATTINY85V-10SU数据手册
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101
2586M–AVR–07/10
ATtiny25/45/85
13.2.1 Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A -
OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the
PB1(OC1A).
When the counter value match the content of OCR1A, the OC1A and output is set or cleared
according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as
shown in Table 13-1.
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output
compare register OCR1C, and starting from $00 up again. A compare match with OCR1C will
set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.
Note that in PWM mode, writing to the Output Compare Register OCR1A, the data value is first
transferred to a temporary location. The value is latched into OCR1A when the Timer/Counter
reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event
of an unsynchronized OCR1A. See Figure 13-4 for an e xample.
Figure 13-4. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A will read the con-
tents of the temporary location. This means that the most recently written value always will read
out of OCR1A.
Table 13-1. Compare Mode Select in PWM Mode
COM1A1 COM1A0 Effect on Output Compare Pin
0 0 OC1A not connected.
0 1 OC1A not connected.
1 0 OC1A cleared on compare match. Set when TCNT1 = $00.
1 1 OC1A set on compare match. Cleared when TCNT1 = $00.
PWM Output OC1A
PWM Output OC1A
Unsynchronized OC1A Latch
Synchronized OC1A Latch
Counter Value
Compare Value
Counter Value
Compare Value
Compare Value changes
Glitch
Compare Value changes
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