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DAC5687 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
封装:
HTQFP-100
描述:
16 位 500 MSPS 2x-8x 内插双通道数模转换器 (DAC)
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P33Hot
典型应用电路图在P65
原理图在P2P20P21P22P23P36P39P51P65
封装尺寸在P74P75P76
焊盘布局在P65
型号编码规则在P1
封装信息在P74P75P76
技术参数、封装参数在P5P6P7P8P9P10P20
应用领域在P1P74P79
电气规格在P6P7P8P9P10P20
导航目录
DAC5687数据手册
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Coarse Mixer (CMIX) Synchronization
B0169-01
PHSTR
PLLLOCK
MUX
CLK1
CLK1C
{PLLVDD,inv_plllock,dual_clk}
clk_in
Clock
Generator
CLK2
CLK2C
clk_out
FIFO
PHSTRSyncto
CoarseMixer
PLL VCO
clk_cmix
Sequencer
Reset
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
sync_cm
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
The coarse mixer implements the f
DAC
/2 and f
DAC
/4 (and – f
DAC
/4) fixed complex mixing operation using simple
complements of the data-path signals to create the proper sequences. The sequences are controlled using a
simple counter, and this counter can be synchronously reset using the PHSTR signal.
Similar to the NCO, the PHSTR signal used by the coarse mixer is from the FIFO output. This introduces the
same uncertainty effect due to the FIFO input-to-output pointer relationship. Bypassing the FIFO and using the
dual external clock mode without FIFO eliminates this uncertainty for systems using multiple DAC5687 devices
when this cannot be tolerated. Using the internal PLL, as with the NCO, allows the complete control and
synchronization of the coarse mixer.
Figure 56. Logic Path for PHSTR Synchronization Signal to CMIX Reset
To enable the PHSTR synchronous reset, the serial interface bit sync_cm in register SYNC_CNTL must be set.
The coarse mixer sequence counter is held in reset when PHSTR is low and operates when PHSTR is high.
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