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DS90UB947TRGCRQ1
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DS90UB947TRGCRQ1数据手册
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DS90UB947-Q1
www.ti.com
SNLS454 NOVEMBER 2014
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Applications Information
The DS90UB947-Q1, in conjunction with the DS90UB940-Q1/DS90UB948-Q1 deserializer, is intended to
interface between a host (graphics processor) and a display, supporting 24-bit color depth (RGB888) and high
definition (1080p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 170 MHz
together with four I2S audio streams when paired with the DS90UB940-Q1/DS90UB948-Q1 deserializer.
9.2 Typical Applications
Bypass capacitors should be placed near the power supply pins. A capacitor and resistor are placed on the PDB
pin to delay the enabling of the device until power is stable. See below for typical STP and coax connection
diagrams.
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 65
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DS90UB947TRGCRQ1 数据手册

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DS90UB947 数据手册

TI(德州仪器)
1080p 双路 FPD-Link III 串行器 64-VQFN -40 to 105
TI(德州仪器)
1080p 双路 FPD-Link III 串行器 64-VQFN -40 to 105
TI(德州仪器)
DS90UB947-Q1 1080p 双路 FPD-Link III 串行器
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