Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > EP2S15F484C3 数据手册 > EP2S15F484C3 数据手册 64/248 页
器件3D模型￥ 2657.266
EP2S15F484C3 数据手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-484
描述:
FPGA - 现场可编程门阵列 FPGA - Stratix II 780 LABs 342 IOs
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P20P25P61P144
封装尺寸在P247
型号编码规则在P7P247
功能描述在P19P20
技术参数、封装参数在P141P142P147P150P151P152P154P155P156P157P158P159
应用领域在P174P175P176P177P178P179
电气规格在P136P149
型号编号列表在P147
导航目录
EP2S15F484C3数据手册
Page:
of 248 Go
若手册格式错乱，请下载阅览PDF原文件
2–46 Altera Corporation
Stratix II Device Handbook, Volume 1 May 2007
Digital Signal Processing Block
Figure 2–30. DSP Block Interface to Interconnect
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed/unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface.
LAB LAB
Row Interface
Block
DSP Block
Row Structure
16
OA[17..0]
OB[17..0]
A[17..0]
B[17..0]
DSP Block to
LAB Row Interface
Block Interconnect Region
36 Inputs per Row 36 Outputs per Row
R4 Interconnect
C4 Interconnect
Direct Link Interconnect
from Adjacent LAB
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
36
36
36
36
Control
12
16
18
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
