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EPM1270F256C3N 数据手册 - Altera（阿尔特拉）
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EPM1270F256C3N数据手册
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2 Altera Corporation
Preliminary
MAX II Device Family
MAX II Power-up
Issue
The MAX II devices may not power-up and enter user mode correctly for
either of the following conditions:
1. V
CCINT
rises slower than the times shown in Table 2.
2. V
CCINT
rise profile exhibits any non-monotonic dips or noise within the
voltage regions shown in Table 2.
This power-up issue is only affected by the V
CCINT
supply; V
CCIO
rise
times or profiles do not affect the MAX II device behavior for this issue.
This issue affects all MAX II devices shown in Table 1.
The failed power-up condition results in all I/O pins remaining tri-state
with weak pull-up resistors even though V
CCINT
has been fully powered.
While in this state, the JTAG port is unresponsive for programming or
boundary scan operations. User mode operation does not begin unless
V
CCINT
power to the MAX II device is recycled.
To ensure successful power-up, Altera recommends (as shown in Table 2)
that you provide a sufficient rise time with a monotonic V
CCINT
rise
profile that contains no dips within the voltage windows.
EPM1270 engineering sample (ES)
devices are not compatible with
EPM1270 production device
Programming Object Files (.pof).
EPM1270 ES Devices (3)
Notes to Ta b le 1 :
(1) See the “MAX II Power-up Issue”section for information on distinguishing revision codes.
(2) Altera is offering permanent recommendations and workarounds for this issue.
(3) This issue is a permanent programming file compatibility restriction.
Table 1. MAX II Device Family Issues (Continued)
Issue Affected Devices Fixed Devices
Table 2. Recommended V
CCINT
Rise Times and V
CCINT
Noise/Dip Free Window
Device and VCCINT Operating
Voltage
Recommended V
CCINT
Rise Time
(1)
Recommended POR Dip/Noise
Free Window
MAX II (3.3V V
CCINT
) <= 1.0 ms 1.5-1.8V
MAX II (2.5V V
CCINT
) <= 750 µs 1.5-1.8V
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