Datasheet 搜索 > CPLD芯片 > Lattice Semiconductor（莱迪思） > GAL22V10D-20LJI 数据手册 > GAL22V10D-20LJI 数据手册 3/23 页
器件3D模型￥ 116.543
GAL22V10D-20LJI 数据手册 - Lattice Semiconductor（莱迪思）
制造商:
Lattice Semiconductor（莱迪思）
分类:
CPLD芯片
封装:
PLCC-28
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
导航目录
GAL22V10D-20LJI数据手册
Page:
of 23 Go
若手册格式错乱，请下载阅览PDF原文件
Specifications GAL22V10
1
228
NC
I/CLK
I
I
I
I
I
I
I
I
NC
NC
NC
GND
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q
I/O/Q
426
25
19
18
21
23
161412
11
9
7
5
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
•E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
ESCRIPTION
Description
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
2
)
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E
2
technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
GAL22V10
High Performance E
2
CMOS PLD
Generic Array Logic™
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
GAL22V10
Top View
PLCC
1
12
13
24
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
6
18
GAL
22V10
DIP
22v10_12
Functional Block Diagram
Pin Configuration
SOIC
GAL22V10
Top View
Lead-Free
Package
Options
Available!
1
12
13
24
I
I
I
I
I
I
I
I
I
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
6
18
I/CLK
I
Vcc
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
ALL DEVICES
DISCONTINUED
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
