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器件3D模型￥ 13.82
HIP4082IBZ 数据手册 - Intersil（英特矽尔）
制造商:
Intersil（英特矽尔）
分类:
FET驱动器
封装:
SOIC-16
描述:
INTERSIL HIP4082IBZ 驱动器芯片, MOSFET, 全桥, 8.5V-15V电源, 1.4A输出, 25ns延迟, SOIC-16
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HIP4082IBZ数据手册
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HIP4082
FN3676 Rev 5.00 Page 6 of 14
September 30, 2015
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO
Low Level Output Voltage V
OL
I
OUT
= 50mA 0.65 1.1 0.5 1.2 V
High Level Output Voltage V
DD
-V
OH
I
OUT
= -50mA 0.7 1.2 0.5 1.3 V
Peak Pullup Current I
O
+V
OUT
= 0V 1.1 1.4 2.5 0.85 2.75 A
Peak Pulldown Current I
O
-V
OUT
= 12V 1.0 1.3 2.3 0.75 2.5 A
Switching Specifications V
DD
= V
AHB
= V
BHB
= 12V, V
SS
= V
AHS
= V
BHS
= 0V, R
DEL
= 100K, C
L
= 1000pF.
PARAMETER SYMBOL TEST CONDITIONS
T
J
= +25°C
T
J
= -5 5°C TO
+150°C
UNITSMIN TYP MAX MIN MAX
Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)
T
LPHL
- 25 50 - 70 ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
T
HPHL
- 55 80 - 100 ns
Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)
T
LPLH
- 40 85 - 100 ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
T
HPLH
- 75 110 - 150 ns
Rise Time T
R
-920-25ns
Fall Time T
F
-920-25ns
Minimum Input Pulse Width T
PWIN-ON/OFF
50 - - 50 - ns
Output Pulse Response to 50 ns Input Pulse
T
PWOUT
63 80 ns
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
T
DISLOW
- 50 80 - 90 ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
T
DISHIGH
- 75 100 - 125 ns
Disable Turn-on Propagation Delay
(DIS - ALO & BLO)
T
DLPLH
- 40 70 - 100 ns
Disable Turn-on Propagation Delay
(DIS- AHO & BHO)
T
DHPLH
R
DEL
= 10K - 1.2 2 - 3 s
Refresh Pulse Width (ALO & BLO) T
REF-PW
375 580 900 350 950 ns
TRUTH TABLE
INPUT OUTPUT
ALI, BLI AHI, BHI VDDUV VHBUV DIS ALO, BLO AHO, BHO
XXXX1 0 0
XX1XX 0 0
0X010 0 0
1X0X0 1 0
01000 0 1
00000 0 0
NOTE: X signifies that input can be either a “1” or “0”.
Electrical Specifications V
DD
= V
AHB
= V
BHB
= 12V, V
SS
= V
AHS
= V
BHS
= 0V, R
DEL
= 100K (Continued)
PARAMETER SYMBOL TEST CONDITIONS
T
J
= +25°C
T
J
= -55°C
TO +150°C
UNITSMIN TYP MAX MIN MAX
HIP4082
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