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L6599DTR 数据手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
电源监控芯片
封装:
SO-16
描述:
L6599系列 16 V 5 mA 半桥 双端 PWM控制器 - SOIC-16N
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L6599DTR数据手册
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Typical system block diagram L6599
6/36
3 Typical system block diagram
Figure 3. Typical system block diagram
N. Name Function
11 LVG
Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.8 A min. sink
peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to
GND during UVLO.
12 V
CC
Supply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a
small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for
the signal part of the IC.
13 N.C.
High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and
ease compliance with safety regulations (creepage distance) on the PCB.
14 OUT
High-side gate-drive floating ground. Current return for the high-side gate-drive current.
Layout carefully the connection of this pin to avoid too large spikes below ground.
15 HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min. source and 0.8A min.
sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally
connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.
16 VBOOT
High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between
this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase
with the low-side gate-drive. This patented structure replaces the normally used external
diode.
Table 2. Pin functions (continued)
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