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MAX3815CCM 数据手册 - Maxim Integrated（美信）
制造商:
Maxim Integrated（美信）
封装:
HTFQFP
描述:
TMDS数字视频均衡器，用于DVI / HDMI电缆 TMDS Digital Video Equalizer for DVI/HDMI Cables
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MAX3815CCM数据手册
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MAX3815
TMDS Digital Video Equalizer for DVI/HDMI
Cables
_______________________________________________________________________________________
5
-1.0
-0.7
-0.8
-0.9
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
04020 60 80 100 120
EQCONTROL VOLTAGE (RELATIVE TO V
CC
)
vs. CABLE LENGTH (MANUAL EQ CONTROL)
MAX3815 toc13
CABLE LENGTH (ft)
EQCONTROL VOLTAGE (V)
CABLE IS TENSOLITE TWIN-AX
28 AWG WITH APPROXIMATELY
0.34dB OF LOSS PER FOOT AT
825MHz
RESIDUAL JITTER
AT 1.65Gbps
EQCONTROL VOLTAGE
0
60
40
20
80
100
120
140
160
180
200
RESIDUAL JITTER (ps
P-P
)
EQUALIZER OUTPUT EYE AFTER 120ft
OF CABLE (DATA RATE = 1.65Gbps)
MAX3815 toc14
CABLE IS TENSOLITE
TWIN-AX 28 AWG
200mV/div
100ps/div
0
100
50
200
150
300
250
350
0406020 80 100 120
LOSS-OF-CLOCK ASSERT THRESHOLD
vs. CABLE LENGTH
MAX3815 toc15
CABLE LENGTH (ft)
DIFFERENTIAL CLOCK AMPLITUDE (mV
P-P
)
165MHz CLOCK FREQUENCY
25MHz CLOCK FREQUENCY
CABLE IS TENSOLITE TWIN-AX 28 AWG
Typical Operating Characteristics (continued)
(Typical values are at V
CC
= +3.3V, T
A
= +25°C, data pattern = 2
7
- 1 PRBS + 20 ones + 2
7
- 1 PRBS (inverted) + 20 zeros, unless
otherwise noted.)
Pin Description
PIN NAME FUNCTION
1, 4, 5, 8, 9,
12, 13, 16,
38, 41, 43, 44
V
CC
Supply Voltage. All pins must be connected to V
CC
.
2 RX0_IN- Negative Data Input, CML
3 RX0_IN+ Positive Data Input, CML
6 RX1_IN- Negative Data Input, CML
7 RX1_IN+ Positive Data Input, CML
10 RX2_IN- Negative Data Input, CML
11 RX2_IN+ Positive Data Input, CML
14 RXC_IN+ Positive Clock Input, CML
15 RXC_IN- Negative Clock Input, CML
17 EQCONTROL
Equalizer Control. This pin allows the user to control the equalization level of the MAX3815. Connect
the pin to GND for automatic operation. Set the voltage to V
CC
/ 2 for minimum equalization, or set
the voltage between V
CC
- 1V to V
CC
for manual equalization. See the Typical Operating
Characteristics for more information.
18 CLKLOS
Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input TMDS
clock from the cable.
19 PWRDWN
Power-Down Input, LVTTL. This input allows the IC to be powered down to conserve power. Connect
high for normal operation. Pull low for power-down mode.
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