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器件3D模型￥ 1.533
MC14049UBDTR2G 数据手册 - ON Semiconductor（安森美）
制造商:
ON Semiconductor（安森美）
分类:
逻辑芯片
封装:
TSSOP-16
描述:
六位缓冲器
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P2Hot
典型应用电路图在P2
原理图在P2
封装尺寸在P5P6P7
焊盘布局在P5P6
型号编码规则在P1P3P7
标记信息在P1P7
封装信息在P3
技术参数、封装参数在P1P3
应用领域在P1P3
电气规格在P2
型号编号列表在P1
导航目录
MC14049UBDTR2G数据手册
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若手册格式错乱，请下载阅览PDF原文件
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 9
1 Publication Order Number:
MC14049UB/D
MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic−level conversion using only one
supply voltage, V
DD
. The input−signal high level (V
IH
) can exceed the
V
DD
supply voltage for logic−level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS−to−TTL/DTL
converters (V
DD
= 5.0 V, V
OL
v 0.4 V, I
OL
≥ 3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
Features
• High Source and Sink Currents
• High−to−Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• Meets JEDEC UB Specifications
• V
IN
can exceed V
DD
• Improved ESD Protection on All Inputs
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
Input Voltage Range
(DC or Transient)
−0.5 to +18.0 V
V
out
Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+0.5
V
I
in
Input Current
(DC or Transient) per Pin
± 10 mA
I
out
Output Current
(DC or Transient) per Pin
+45 mA
P
D
Power Dissipation, per Package (Note 1)
Plastic
SOIC
825
740
mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature (8−Second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V
SS
pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high−impedance circuit. For proper operation, the ranges
V
SS
v V
in
v 18 V and V
SS
v V
out
v V
DD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
14049UG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
MC14049UB
ALYWG
1
16
1
16
14
049UB
ALYW G
G
1
16
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
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