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MC68332ACAG25
器件3D模型
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MC68332ACAG25数据手册
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REGISTER SUMMARY MC68332
D-8 USER’S MANUAL
D.2.6 PORTE0/PORTE1 — Port E Data Register $YFFA11, $YFFA13
PORTE is an internal data latch that can be accessed at two locations. PORTE can be
read or written at any time. If a pin in I/O port E is configured as an output, the corre-
sponding bit value is driven out on the pin. When a pin is configured for output, a read
of PORTE returns the latched bit value; when a pin is configured for input, a read re-
turns the pin logic level.
D.2.7 DDRE — Port E Data Direction Register $YFFA15
Bits in this register control the direction of the port E pin drivers when pins are config-
ured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit
configures the corresponding pin as an input. This register can be read or written at
any time.
D.2.8 PEPAR — Port E Pin Assignment Register $YFFA17
Bits in this register determine the function of port E pins. Setting a bit assigns the cor-
responding pin to a bus control signal; clearing a bit assigns the pin to I/O port E.
15 8 7 6 5 4 3 2 1 0
NOT USED PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
RESET:
U U U U U U U U
15 8 7 6 5 4 3 2 1 0
NOT USED DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0
RESET:
0 0 0 0 0 0 0 0
15 8 7 6 5 4 3 2 1 0
NOT USED PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
RESET:
DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8
Port E Pin Assignments
PEPAR Bit Port E Signal Bus Control Signal
PEPA7 PE7 SIZ1
PEPA6 PE6 SIZ0
PEPA5 PE5 AS
PEPA4 PE4 DS
PEPA3 PE3 RMC
PEPA2 PE2 AVEC
PEPA1 PE1 DSACK1
PEPA0 PE0 DSACK0
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Freescale Semiconductor, Inc.
For More Information On This Product,
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MC68332ACAG25 数据手册

Freescale(飞思卡尔)
265 页 / 2.9 MByte
Freescale(飞思卡尔)
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MC68332 数据手册

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