Datasheet 搜索 > 微控制器 > Freescale（飞思卡尔） > MC68332GCEH25 数据手册 > MC68332GCEH25 数据手册 49/265 页
器件3D模型￥ 7.236
MC68332GCEH25 数据手册 - Freescale（飞思卡尔）
制造商:
Freescale（飞思卡尔）
分类:
微控制器
封装:
PQFP-132
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P22P26P28P29P40P82P91P92P98P206P207P218Hot
原理图在P26P27P42P49P91P100P119P123P128P145P146P155
封装尺寸在P208
型号编码规则在P205P206P207P208P209P210P211P212P260
应用领域在P25
电气规格在P51P63P72P84P89P172P175P176P177P178P179P180
导航目录
MC68332GCEH25数据手册
Page:
of 265 Go
若手册格式错乱，请下载阅览PDF原文件
MC68332 SYSTEM INTEGRATION MODULE
USER’S MANUAL 4-9
4.2.13 Freeze Operation
The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in-
ternally by the CPU32 if a breakpoint occurs while background mode is enabled. When
FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt
timer are affected. The halt monitor and spurious interrupt monitor continue to operate
normally. Setting the freeze bus monitor (FRZBM) bit in the SIMCR disables the bus
monitor when FREEZE is asserted, and setting the freeze software watchdog
(FRZSW) bit disables the software watchdog and the periodic interrupt timer when
FREEZE is asserted. When FRZSW is set, FREEZE assertion must be at least two
times the PIT clock source period to ensure an accurate number of PIT counts.
4.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an
external peripheral bus. Because the MCU is a fully static design, register and memory
contents are not affected when the clock rate changes. System hardware and software
support changes in clock rate during operation.
The system clock signal can be generated in one of three ways. An internal phase-
locked loop can synthesize the clock from either an internal reference or an external
reference, or the clock signal can be input from an external frequency source. Keep
these clock sources in mind while reading the rest of this section. Figure 4-4 is a block
diagram of the system clock. Refer to APPENDIX A ELECTRICAL CHARACTERIS-
TICS for clock specifications.
Figure 4-4 System Clock Block Diagram
32 PLL BLOCK
CLKOUT
PHASE
COMPARATOR
LOW-PASS
FILTER
VCO
CRYSTAL
OSCILLATOR
SYSTEM
CLOCK
SYSTEM CLOCK CONTROL
FEEDBACK DIVIDER
W
X
Y
EXTAL XTAL XFC
V
DDSYN
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
