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MC9S08AC128CFUE 数据手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
8位微控制器
封装:
QFP-64
描述:
NXP MC9S08AC128CFUE 微控制器, 8位, Flexis - S08AC, 40 MHz, 128 KB, 8 KB, 64 引脚, QFP
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MC9S08AC128CFUE数据手册
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A transient pin current greater than -20 mA can momentarily trigger the high I
DD
condition. The
supply current will recover after the transient current decays.
Workaround: This condition requires a negative current that is many times greater than the maximum
negative DC injection current specification of -0.2 mA per pin. Proper resistor selection to limit
the injection current will prevent this condition when the pin is configured as an input.
SE181-ICG-RST: ICG HGO = 1 long reset
Errata type: Silicon
Affects: ICG, Reset
Description: When the ICG (Internal Clock Generator) is configured in FBE (FLL bypassed external) mode
and the HGO (high gain option) bit is set, an internally generated reset may cause a reset (low)
pulse that is much longer than a typical 9 µs to 20 µs pulse width. The Reset low time can
extend to many seconds at low temperatures (<0°C) if the oscillations on the EXTAL pin are
attenuated due to series resistance or oscillator loading.
The ICG contains logic to switch from the external clock to an internal clock when Reset is
asserted (low) in FBE mode. This switch requires 2 full clocks to operate properly. However, in
FBE mode with HGO = 1, the external clock input signal (EXTAL) may not have sufficient
voltage swing, particularly the low level, to properly clock the logic just after Reset is asserted.
Workaround: The best workaround is to use HGO = 0 if FBE mode is desired. Note that when HGO = 0 is
selected, the series resistor (RS) must be 0 Ω. This workaround is effective because the
oscillation levels at the EXTAL pin are sufficient to clock the internal logic when Reset is
asserted.
An alternate workaround is to use HGO = 1 with RS = 0 Ω and crystal/resonator load
components that guarantee that the EXTAL low level is below 0.5 V.
SE157-ADC-INCORRECT-DATA: Boundary case may result in incorrect data being
read in 10-bit modes
Errata type: Silicon
Affects: ADC
Description: In normal 10-bit operation of the ADC, the coherency mechanism will freeze the conversion
data such that when the high byte of data is read, the low byte of data is frozen, ensuring that
the high and low bytes represent result data from the same conversion.
In the errata case, there is a single-cycle (bus clock) window per conversion cycle when a high
byte may be read on the same cycle that subsequent a conversion is completing. Although
extremely rare due to the precise timing required, in this case, it is possible that the data
transfer occurs, and the low byte read may be from the most recently completed conversion.
In systems where the ADC is running off the bus clock, and the data is read immediately upon
completion of the conversion, the errata will not occur. Also, in single conversion mode, if the
data is read prior to starting a new conversion, then the errata will not occur.
The errata does not impact 8-bit operation.
Introducing significant delay between the conversion completion and reading the data, while a
following conversion is executing/pending, could increase the probability for the errata to
occur. Nested interrupts, significant differences between the bus clock and the ADC clock ,
and not handling the result register reads consecutively, can increase the delay and therefore
the probability of the errata occurring.
Mask Set Errata for Mask 1M72Y, Rev 0, 10/2013
2 Freescale Semiconductor, Inc.
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