Datasheet 搜索 > 微控制器 > Freescale（飞思卡尔） > MC9S12XDT512CAG 数据手册 > MC9S12XDT512CAG 数据手册 814/1348 页
器件3D模型￥ 7.268
MC9S12XDT512CAG 数据手册 - Freescale（飞思卡尔）
制造商:
Freescale（飞思卡尔）
分类:
微控制器
封装:
LQFP-144
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P49P50P51P694P746P808P809P810P811P812P813P814Hot
典型应用电路图在P98P1268
原理图在P34P35P36P81P120P125P126P160P161P185P310P351
封装尺寸在P1288P1289P1290P1291
型号编码规则在P1306
封装信息在P1243
功能描述在P98P122P152P180P202P350P380P409P421P456P493P528
技术参数、封装参数在P1239
电气规格在P122P799P1237P1238P1239P1240P1241P1242P1243P1244P1245P1246
型号编号列表在P1306
导航目录
MC9S12XDT512CAG数据手册
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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
816 Freescale Semiconductor
J
PJ7
TXCAN4 O MSCAN4 transmit pin
GPIO
SCL0 O Inter Integrated Circuit 0 serial clock line
TXCAN0 O MSCAN0 transmit pin
GPIO/KWJ7 I/O General-purpose I/O with interrupt
PJ6
RXCAN4 I MSCAN4 receive pin
SDA0 I/O Inter Integrated Circuit 0 serial data line
RXCAN0 I MSCAN0 receive pin
GPIO/KWJ6 I/O General-purpose I/O with interrupt
PJ5
SCL1 O Inter Integrated Circuit 1 serial clock line
CS2 O Chip select 2
GPIO/KWJ7 I/O General-purpose I/O with interrupt
PJ4
SDA1 I/O Inter Integrated Circuit 1 serial data line
CS0 O Chip select 0
GPIO/KWJ6 I/O General-purpose I/O with interrupt
PJ2
CS1 O Chip select 1
GPIO/KWJ2 I/O General-purpose I/O with interrupt
PJ1
TXD2 O Serial Communication Interface 2 transmit pin
GPIO/KWJ1 I/O General-purpose I/O with interrupt
PJ0
RXD2 I Serial Communication Interface 2 receive pin
CS3 O Chip select 3
GPIO/KWJ0 I/O General-purpose I/O with interrupt
AD0 PAD[07:00]
GPIO I/O General-purpose I/O
GPIO
AN[7:0] I ATD0 analog inputs
AD1 PAD[23:08]
GPIO I/O General-purpose I/O
GPIO
AN[15:0] I ATD1 analog inputs
1
Function active when RESET asserted.
2
Only available in emulation modes or in Special Test Mode with IVIS on.
3
Refer also to Table 22-70 and S12X_EBI section.
Table 22-1. Pin Functions and Priorities (Sheet 7 of 7)
Port Pin Name
Pin Function
and Priority
I/O Description
Pin Function
after Reset
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