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MPC8306VMADDCA 数据手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-369
描述:
PowerPC系列 266MHz
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P2
封装尺寸在P49P50
型号编码规则在P72P73
标记信息在P73
技术参数、封装参数在P2P3P4P5P6P7P8P9P10P11P12P13
电气规格在P7P8P9P11P12P13P14P18P21P22P26P27
型号编号列表在P72
导航目录
MPC8306VMADDCA数据手册
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若手册格式错乱，请下载阅览PDF原文件
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor 3
Overview
In summary, the MPC8306 provides users with a highly integrated, fully programmable communications
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
1.1 Features
The major features of the device are as follows:
• e300c3 Power Architecture processor core
— Enhanced version of the MPC603e core
— High-performance, superscalar processor core with a four-stage pipeline and low interrupt
latency times
— Floating-point, dual integer units, load/store, system register, and branch processing units
— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
— Dynamic power management
— Enhanced hardware program debug features
— Software-compatible with Freescale processor families implementing Power Architecture
technology
— Separate PLL that is clocked by the system bus clock
— Performance monitor
• QUICC Engine block
— 32-bit RISC controller for flexible support of the communications peripherals with the
following features:
– One clock per instruction
– Separate PLL for operating frequency that is independent of system’s bus and e300 core
frequency for power and performance optimization
– 32-bit instruction object code
– Executes code from internal IRAM
– 32-bit arithmetic logic unit (ALU) data path
– Modular architecture allowing for easy functional enhancements
– Slave bus for CPU access of registers and multiuser RAM space
– 48 Kbytes of instruction RAM
– 16 Kbytes of multiuser data RAM
– Serial DMA channel for receive and transmit on all serial channels
— Five unified communication controllers (UCCs) supporting the following protocols and
interfaces:
– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.
– IEEE Std. 1588™ support
– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)
– HDLC Bus (bit rate up to 10 Mbps)
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