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MT48LC16M16A2P-75 IT:D 数据手册 - Micron（镁光）
制造商:
Micron（镁光）
分类:
存储芯片
封装:
TSOP-54
Pictures:
3D模型
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MT48LC16M16A2P-75 IT:D数据手册
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SDR SDRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
Features
•
PC100- and PC133-compliant
•
Fully synchronous; all signals registered on positive
edge of system clock
•
Internal, pipelined operation; column address can
be changed every clock cycle
•
Internal banks for hiding row access/precharge
•
Programmable burst lengths: 1, 2, 4, 8, or full page
•
Auto precharge, includes concurrent auto pre-
charge and auto refresh modes
•
Self refresh mode (not available on AT devices)
•
Auto refresh
–
64ms, 8192-cycle (commercial and industrial)
–
16ms, 8192-cycle (automotive)
•
LVTTL-compatible inputs and outputs
•
Single +3.3V ±0.3V power supply
Table 1: Address Table
Parameter 64 Meg x 4 32 Meg x 8
16 Meg
x 16
Configuration 16 Meg x 4
x 4 banks
8 Meg x 8 x
4 banks
4 Meg x 16
x 4 banks
Refresh count 8K 8K 8K
Row addressing 8K A[12:0] 8K A[12:0] 8K A[12:0]
Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0]
Column
addressing
2K A[9:0],
A11
1K A[9:0] 512 A[8:0]
Table 2: Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
Clock
Frequency
Access Time
Setup
Time
Hold
TimeCL = 2 CL = 3
-6A 167 MHz
–
5.4ns 1.5ns 0.8ns
-7E 143 MHz
–
5.4ns 1.5ns 0.8ns
-75 133 MHz
–
5.4ns 1.5ns 0.8ns
-7E 133 MHz 5.4ns
–
1.5ns 0.8ns
-75 100 MHz 6ns
–
1.5ns 0.8ns
Options Marking
•
Configurations
–
64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4
–
32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8
–
16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16
•
Write recovery (
t
WR)
–
t
WR = 2 CLK
1
A2
•
Plastic package – OCPL
2
–
54-pin TSOP II OCPL
2
(400 mil)
(standard)
TG
–
54-pin TSOP II OCPL
2
(400 mil)
Pb-free
P
–
60-ball FBGA (x4, x8) (8mm x 16mm) FB
–
60-ball FBGA (x4, x8) (8mm x 16mm)
Pb-free
BB
–
54-ball VFBGA (x16) (8mm x 14 mm) FG
–
54-ball VFBGA (x16) (8mm x 14 mm)
Pb-free
BG
•
Timing – cycle time
–
6ns @ CL = 3 (x8, x16 only) -6A
–
7.5ns @ CL = 3 (PC133) -75
–
7.5ns @ CL = 2 (PC133) -7E
•
Self refresh
–
Standard None
–
Low power L
3
•
Operating temperature range
–
Commercial (0˚C to +70˚C) None
–
Industrial (–40˚C to +85˚C) IT
–
Automotive (–40˚C to +105˚C) AT
3
•
Revision :D
Notes:
1. See Micron technical note TN-48-05 on
Micron's Web site.
2. Off-center parting line.
3. Contact Micron for availability.
256Mb: x4, x8, x16 SDRAM
Features
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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