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NC7SZ14 数据手册 - Fairchild（飞兆/仙童）
制造商:
Fairchild（飞兆/仙童）
描述:
TinyLogic UHS逆变器与施密特触发器输入 TinyLogic UHS Inverter with Schmitt Trigger Input
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NC7SZ14数据手册
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© 2003 Fairchild Semiconductor Corporation DS012176 www.fairchildsemi.com
October 1996
Revised May 2003
NC7SZ14 TinyLogic
UHS Inverter with Schmitt Trigger Input
NC7SZ14
TinyLogic
UHS Inverter with Schmitt Trigger Input
General Description
The NC7SZ14 is a single Inverter with Schmitt Trigger
input from Fairchild’s Ultra High Speed Series of
TinyLogic
. The device is fabricated with advanced CMOS
technology to achieve ultra high speed with high output
drive while maintaining low static power dissipation over a
very broad V
CC
operating range. The device is specified to
operate over the 1.65V to 5.5V V
CC
range. The input and
output are high impedance when V
CC
is 0V. Inputs tolerate
voltages up to 6V independent of V
CC
operating voltage.
Features
■ Space saving SOT23 or SC70 5-lead package
■ Ultra small MicroPak
leadless package
■ Ultra High Speed; t
PD
3.7 ns Typ into 50 pF at 5V V
CC
■ High Output Drive; ±24 mA at 3V V
CC
■ Broad V
CC
Operating Range; 1.65V to 5.5V
■ Matches the performance of LCX when operated at
3.3V V
CC
■ Power down high impedance inputs/output
■ Overvoltage Tolerant inputs facilitate 5V to 3V
translation
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Logic Symbol
IEEE/IEC
Pin Descriptions
Function Table
Y = A
H = HIGH Logic Level
L = LOW Logic Level
Connection Diagrams
Pin Assignments for SOT23 and SC70
(Top View)
Pad Assignments for MicroPak
(Top Thru View)
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MIcroPak is a trademark of Fairchild Semiconductor Corporation.
Order Package Product Code
Package Description Supplied As
Number Number Top Mark
NC7SZ14M5X MA05B 7Z14 5-Lead SOT23, JEDEC MO-178, 1.6mm 3k Units on Tape and Reel
NC7SZ14P5X MAA05A Z14 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3k Units on Tape and Reel
NC7SZ14L6X MAC06A B6 6-Lead MicroPak, 1.0mm Wide 5k Units on Tape and Reel
Pin Names Description
A Input
Y Output
NC No Connect
Input Output
AY
LH
HL
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