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BALANCE
VCC+
IN1í
IN1+
VCCí
COMP/BAL
OUT
COMP
RG
RIN
RF
GND
VIN
VS-GND
VS+
GND
Run the input traces as far
away from the supply lines
as possible
Only needed for
dual-supply
operation
Place components close to
device and to each other to
reduce parasitic errors
Use low-ESR, ceramic
bypass capacitor
(or GND for single supply) Ground (GND) plane on another layerVOUT
+
RIN
RG
RF
VOUT
VIN
NE5534
,
NE5534A
,
SA5534
,
SA5534A
www.ti.com
SLOS070D JULY 1979REVISED NOVEMBER 2014
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques (SLOA089).
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as
opposed to in parallel, with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in .
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Figure 15. Operational Amplifier Schematic for Noninverting Configuration
Figure 16. Operational Amplifier Board Layout for Noninverting Configuration
Copyright © 1979–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
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NE5534PE4 数据手册

TI(德州仪器)
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NE5534 数据手册

TI(德州仪器)
Texas Instruments
TI(德州仪器)
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TI(德州仪器)
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TI(德州仪器)
TEXAS INSTRUMENTS  NE5534ADR  运算放大器, 单路, 10 MHz, 1个放大器, 13 V/µs, ± 5V 至 ± 15V, SOIC, 8 引脚
TI(德州仪器)
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TI(德州仪器)
Texas Instruments
ON Semiconductor(安森美)
NE5534、SA5534、低噪声运算放大器,ON Semiconductor小信号带宽:10 MHz 输入噪声电压:4 nV/√Hz 直流电压增益:100000 适用于音频应用 ### 运算放大器,ON Semiconductor
ON Semiconductor(安森美)
NE5534、SA5534、低噪声运算放大器,ON Semiconductor小信号带宽:10 MHz 输入噪声电压:4 nV/√Hz 直流电压增益:100000 适用于音频应用 ### 运算放大器,ON Semiconductor
ON Semiconductor(安森美)
ON SEMICONDUCTOR  NE5534DG  运算放大器, 单路, 10 MHz, 1个放大器, 13 V/µs, ± 3V 至 ± 20V, SOIC, 8 引脚
ON Semiconductor(安森美)
ON SEMICONDUCTOR  NE5534ADG  运算放大器, 单路, 10 MHz, 1个放大器, 13 V/µs, ± 3V 至 ± 20V, SOIC, 8 引脚
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