Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC18F27J53-I/SS 数据手册 > PIC18F27J53-I/SS 数据手册 3/12 页
器件3D模型￥ 53.005
PIC18F27J53-I/SS 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
SSOP-28
描述:
MICROCHIP PIC18F27J53-I/SS 微控制器, 8位, 闪存, AEC-Q100, PIC18FxxJxx, 48 MHz, 128 KB, 3.7109 KB, 28 引脚, SSOP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
技术参数、封装参数在P9
电气规格在P6P8P9
导航目录
PIC18F27J53-I/SS数据手册
Page:
of 12 Go
若手册格式错乱，请下载阅览PDF原文件
2010 Microchip Technology Inc. DS80506C-page 3
PIC18F47J53 FAMILY
Silicon Errata Issues
1. Module: Charge Time Measurement Unit
(CTMU)
When using the CTMU, the constant current
source may not output if the internal band gap
reference is not enabled.
Work around
Before using the CTMU, the internal band gap ref-
erence module should be manually enabled by
setting the VBGEN bit to ‘1’ (ANCON1<7> = 1).
Affected Silicon Revisions
2. Module: Phase Locked Loop (PLL)
When OSCCON<6:4> are configured to settings
other than a 4 MHz or 8 MHz INTOSC post-
scaler, the PLLEN bit (OSCTUNE<6>) is forced
to ‘0’, even if firmware tries to set the PLLEN bit.
This may prevent firmware from enabling the
PLL.
Work around
Before attempting to set the PLLEN bit, config-
ure OSCCON<6:4> to ‘0b110’ or ‘0b111’ to
select the 4 MHz or 8 MHz INTOSC postscaler.
Affected Silicon Revisions
3. Module: Analog-to-Digital Converter
(ADC)
At the beginning of sample acquisition, one or
more small pull-up pulses (approximately 25 ns
long) may output to the currently selected ANx
analog channel. These pulses can lead to a pos-
itive offset error when the analog signal voltage
is near V
SS and the external analog signal driver
is unable to dissipate the added pull-up voltage
before the A/D conversion occurs.
Work around
Do one or more of the following:
• Use the “0 T
AD” A/D acquisition time setting to
start the next sample acquisition period imme-
diately following an A/D conversion
completion.
This allows the external analog signal driver
more time to dissipate the pull-up pulses that
occur when the sample acquisition is started.
• Use a longer A/D acquisition time setting to
provide time for the external analog signal
driver to dissipate the pull-up pulse voltage.
• Use low-impedance, active analog signal
drivers to reduce the time needed to dissipate
the pull-up pulse voltage.
• Experiment with external filter capacitor val-
ues to avoid allowing the pull-up voltage offset
to affect the final voltage that gets converted.
Small filter capacitor values (or none at all) will
allow time for the external analog signal driver to
dissipate the pull-up voltage quickly. Alternately,
large filter capacitor values will prevent the short
pull-up pulses from increasing the final voltage
enough to cause an A/D conversion error.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
A1
X
A1
X
A1
X
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
