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PIC24FJ64GA705-I/M4数据手册
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2016 Microchip Technology Inc. DS30010118B-page 19
PIC24FJ256GA705 FAMILY
FIGURE 1-1: PIC24FJ256GA705 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
16
16
8
Interrupt
Controller
EDS and
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
HLVD &
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulators
Voltage
V
CAP
PORTA
(1)
PORTC
(1)
(12 I/Os)
(8 I/Os)
PORTB
(16 I/Os)
Note 1:
Not all I/O pins or features are implemented on all device pinout configurations. See Ta bl e 1-3 for specific implementations by pin count.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
3:
Some peripheral I/Os are only accessible through remappable pins.
Comparators
(3)
Timer2/3
(3)
Timer1
RTCC
IC
A/D
12-Bit
OC/PWM
SPI
I2C1-2
EPMP/PSP
1-3
(3)
IOCs
(1)
UART
REFO
1-3
(3)
1-2
(3)
1-3
(3)
CTMU
Space
Program Memory/
CLC1-2
(1)
DMA
Controller
Data
DMA
Data Bus
16
Ta b le Dat a
Access Control
MCCP1/2/3
PCL
BOR
(2)
Read AGU
Write AGU

PIC24FJ64GA705-I/M4 数据手册

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PIC24FJ64GA705 数据手册

Microchip(微芯)
Microchip(微芯)
16位微控制器 - MCU 16-bit, 16 MIPS, 64KB Flash, 16KB RAM
Microchip(微芯)
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