Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC32MX440F256H-80I/PT 数据手册 > PIC32MX440F256H-80I/PT 数据手册 89/214 页
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PIC32MX440F256H-80I/PT 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
TQFP-64
描述:
MICROCHIP PIC32MX440F256H-80I/PT 微控制器, 32位, 常规性能, PIC32, 80 MHz, 256 KB, 32 KB, 64 引脚, TQFP
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引脚图在P6P7P8P9P12P13P14P15P22P23P24P25Hot
原理图在P21P37P87P95P97P101P103P105P106P107P109P111
封装尺寸在P192P204
标记信息在P191P204
封装信息在P4P5P152P191P193P194P195P196P198P199P200P201
功能描述在P43P119
技术参数、封装参数在P152P157P158P160P161P163P179P180P188P206P208
电气规格在P32P102P138P158P188P204P206P208
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PIC32MX440F256H-80I/PT数据手册
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© 2011 Microchip Technology Inc. DS61143H-page 89
PIC32MX3XX/4XX
7.0 INTERRUPT CONTROLLER
PIC32MX3XX/4XX devices generate interrupt requests
in response to interrupt events from peripheral mod-
ules. The Interrupt Control module exists externally to
the CPU logic and prioritizes the interrupt events before
presenting them to the CPU.
The PIC32MX3XX/4XX interrupts module includes the
following features:
• Up to 96 interrupt sources
• Up to 64 interrupt vectors
• Single and Multi-Vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Module Freeze in Debug mode
• Seven user-selectable priority levels for each
vector
• Four user-selectable subpriority levels within each
priority
• Dedicated shadow set for highest priority level
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
FIGURE 7-1: INTERRUPT CONTROLLER MODULE
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller” (DS61108) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Interrupt Controller
Interrupt Requests
Vector Number
CPU Core
Priority Level
Shadow Set Number
Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and
bits) are associated with the CPU. Details about them are available in Section 3.0 “CPU”.
To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this
section, and all other sections of this manual, are signified by uppercase letters only. The CPU register
names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register;
whereas, IntCtl is a CPU register.
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