Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC32MX460F512L-80I/PT 数据手册 > PIC32MX460F512L-80I/PT 数据手册 95/214 页
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PIC32MX460F512L-80I/PT 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
TQFP-100
描述:
MICROCHIP PIC32MX460F512L-80I/PT 微控制器, 32位, 常规性能, PIC32, 80 MHz, 512 KB, 32 KB, 100 引脚, TQFP
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引脚图在P6P7P8P9P12P13P14P15P22P23P24P25Hot
原理图在P21P37P87P95P97P101P103P105P106P107P109P111
封装尺寸在P192P204
标记信息在P191P204
封装信息在P4P5P152P191P193P194P195P196P198P199P200P201
功能描述在P43P119
技术参数、封装参数在P152P157P158P160P161P163P179P180P188P206P208
电气规格在P32P102P138P158P188P204P206P208
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PIC32MX460F512L-80I/PT数据手册
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© 2011 Microchip Technology Inc. DS61143H-page 95
PIC32MX3XX/4XX
9.0 PREFETCH CACHE
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1 Features
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to hold
repeated instructions
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch
FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) of the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
CTRL
RDATA
Prefetch
Prefetch
Hit Logic
Cache
Line
Address
Encode
Cache Line
FSM
CTRL RDATA
Tag Logic
Bus Control
Cache Control
Prefetch Control
Hit LRU
Miss LRU
BMX/CPU
BMX/CPU
CTRL
PFM
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