Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC32MX795F512H-80I/MR 数据手册 > PIC32MX795F512H-80I/MR 数据手册 41/441 页
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PIC32MX795F512H-80I/MR 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
QFN-64
描述:
MICROCHIP PIC32MX795F512H-80I/MR 微控制器, 32位, 图形接口, PIC32, 80 MHz, 512 KB, 128 KB, 64 引脚, QFN
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引脚图在P38P423P428P431Hot
原理图在P25P41P69P95P101P111P157P167P171P172P177P181
封装尺寸在P403P430
标记信息在P401P402P430
封装信息在P2P3P4P352P401P403P404P405P407P409P410P411
功能描述在P47P221P279P323P327P333
技术参数、封装参数在P353P360P361P362P364P365P366P368P386P388P389P397
电气规格在P38P158P362P397P421P425P428P429P430P432
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PIC32MX795F512H-80I/MR数据手册
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若手册格式错乱，请下载阅览PDF原文件
2009-2016 Microchip Technology Inc. DS60001156J-page 41
PIC32MX5XX/6XX/7XX
3.0 CPU
The MIPS32
®
M4K
®
Processor core is the heart of the
PIC32MX5XX/6XX/7XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1 Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
• MIPS16e
®
code compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8-bit and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple dual bus interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
• Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
• Power control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
-Breakpoints
- PC tracing with trace compression
FIGURE 3-1: MIPS32
®
M4K
®
PROCESSOR CORE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS60001113) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site (www.micro-
chip.com/PIC32). Resources for the
MIPS32
®
M4K
®
Processor Core are
available at http://www.imgtec.com.
CPU
MDU
Execution Core
(RF/ALU/Shift)
FMT
TAP
EJTAG
Bus Interface
Power
Management
System
Co-processor
Off-chip Debug Interface
Bus Matrix
Dual Bus Interface
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