Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC32MX795F512L-80I/PT 数据手册 > PIC32MX795F512L-80I/PT 数据手册 143/256 页
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PIC32MX795F512L-80I/PT 数据手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
TQFP-100
描述:
MICROCHIP PIC32MX795F512L-80I/PT 微控制器, 32位, 图形接口, PIC32, 80 MHz, 512 KB, 128 KB, 100 引脚, TQFP
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引脚图在P4P5P6P7P8P9P10P11P12P13P14P15Hot
原理图在P31P49P119P125P127P129P133P135P137P138P139P141
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标记信息在P225P226
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PIC32MX795F512L-80I/PT数据手册
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© 2009-2011 Microchip Technology Inc. DS61156G-page 143
PIC32MX5XX/6XX/7XX
17.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, Analog-to-Digital Converters, etc. The
PIC32 SPI module is compatible with Motorola
®
SPI
and SIOP interfaces.
Following are some of the key features of this module:
• Master and Slave modes support
• Four different clock formats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data
width
• Separate SPI FIFO buffers for receive and
transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
• Operation during CPU Sleep and Idle mode
• Fast bit manipulation using CLR, SET and INV
registers
FIGURE 17-1: SPI MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to
Section 23. “Serial
Peripheral Interface (SPI)” (DS61106) in
the
“PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Internal
Data Bus
SDIx
SDOx
SSx
/FSYNC
SCKx
SPIxSR
bit 0
Shift
Control
Edge
Select
Enable Master Clock
Baud Rate
Slave Select
Sync Control
Clock
Control
Transmit
Receive
and Frame
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
FIFOs Share Address SPIxBUF
SPIxBUF
Generator
PBCLK
WriteRead
SPIxTXB FIFO
SPIxRXB FIFO
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