Datasheet 搜索 > LVDS、M-LVDS、ECL、CML > TI（德州仪器） > SN65LV1224BDBRG4 数据手册 > SN65LV1224BDBRG4 数据手册 1/30 页
器件3D模型￥ 46.374
SN65LV1224BDBRG4 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
LVDS、M-LVDS、ECL、CML
封装:
SSOP-28
描述:
10 MHz至66 MHz的10 ： 1 LVDS串行器/解串器 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
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SN65LV1224BDBRG4数据手册
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SYNC1
SYNC2
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
D
IN9
TCLK_R/F
TCLK
DV
CC
DV
CC
AV
CC
AGND
PWRDN
AGND
D
O
+
D
O
−
AGND
DEN
AGND
AV
CC
DGND
DGND
DB Package
SN65LV1023A
Serializer
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32 31 30 29 28 27 26 25
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D
IN1
D
IN
2
D
IN
3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
AGND
PWRDN
AGND
D
O+
D
O−
AGND
DEN
AGND
RHB Package
SN65LV1023A
Serializer
(Top View)
D
IN0
SYNC2
SYNC1
DV
CC
DV
CC
DV
CC
DV
CC
AV
CC
D
IN9
TCLK_R/F
TCLK
DGND
DGND
DGND
DGND
AV
CC
SN65LV1023A
SN65LV1224B
www.ti.com
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009
10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
Check for Samples: SN65LV1023A SN65LV1224B
1
FEATURES
DESCRIPTION
• 100-Mbps to 660-Mbps Serial LVDS Data
Payload Bandwidth at 10-MHz to 66-MHz
The SN65LV1023A serializer and SN65LV1224B
System Clock
deserializer comprise a 10-bit serdes chipset
designed to transmit and receive serial data over
• Pin-Compatible Superset of
LVDS differential backplanes at equivalent parallel
DS92LV1023/DS92LV1224
word rates from 10 MHz to 66 MHz. Including
• Chipset (Serializer/Deserializer) Power
overhead, this translates into a serial data rate
Consumption <450 mW (Typ) at 66 MHz
between 120-Mbps and 792-Mbps payload encoded
• Synchronization Mode for Faster Lock
throughput.
• Lock Indicator
Upon power up, the chipset link can be initialized via
a synchronization mode with internally generated
• No External Components Required for PLL
SYNC patterns or the deserializer can be allowed to
• 28-Pin SSOP and Space Saving 5 × 5 mm QFN
synchronize to random data. By using the
Packages Available
synchronization mode, the deserializer establishes
• Industrial Temperature Qualified,
lock within specified, shorter time parameters.
T
A
= −40°C to 85°C
The device can be entered into a power-down state
• Programmable Edge Trigger on Clock
when no data transfer is required. Alternatively, a
• Flow-Through Pinout for Easy PCB Layout
mode is available to place the output pins in the
high-impedance state without losing PLL lock.
APPLICATIONS
The SN65LV1023A and SN65LV1224B are
• Wireless Base Station
characterized for operation over ambient air
• Backplane Interconnect
temperature of –40°C to 85°C.
• DSLAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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