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器件3D模型￥ 3.558
SN74HCT125DE4 数据手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
逻辑控制器
封装:
SOIC-14
描述:
具有三态输出的四路总线缓冲门 14-SOIC -40 to 85
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SN74HCT125DE4数据手册
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若手册格式错乱，请下载阅览PDF原文件
SN54HCT125, SN74HCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS069E – NOVEMBER 1988 – REVISED AUGUST 2003
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V
10%
90%
3 V
≈V
CC
V
OL
0 V
Input
Output
Waveform 1
(See Note B)
1.3 V
t
PZL
t
PLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
V
OH
≈0 V
1.3 V
1.3 V
t
PZH
t
PHZ
Output
Waveform 2
(See Note B)
From Output
Under Test
R
L
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER C
L
t
PZH
t
pd
or t
t
t
dis
t
en
t
PZL
t
PHZ
t
PLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
R
L
S1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF
Open Open––
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z
O
= 50 Ω, t
r
= 6 ns, t
f
= 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
C
L
(see Note A)
1.3 V
1.3 V1.3 V
10%10%
90% 90%
3 V
V
OH
V
OL
0 V
t
r
t
f
Input
Output
1.3 V
t
PLH
t
PHL
Figure 1. Load Circuit and Voltage Waveforms
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