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SN74LVC2G04MDCKREP
器件3D模型
11.284
导航目录
  • 典型应用电路图在P2
  • 封装尺寸在P2P7P9P10
  • 型号编码规则在P1P2
  • 标记信息在P2P7
  • 封装信息在P7P8P9P10
  • 技术参数、封装参数在P3
  • 应用领域在P13
  • 电气规格在P5
SN74LVC2G04MDCKREP数据手册
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FEATURES
3
2
4
61
1A 1Y
2Y
GND
2A
DBV PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
61
1A 1Y
2Y
GND
2A
3
2
4
61
1A 1Y
2Y
GND
2A
1A
2A
1Y
2Y
GND
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
1
4
2
3
6
V
CC
V
CC
V
CC
5
V
CC
5
5
5
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G04-EP
DUAL INVERTER GATE
SGLS365 AUGUST 2006
Controlled Baseline I
off
Supports Partial Power-Down-Mode
Operation
One Assembly Site
Latch-Up Performance Exceeds 100 mA Per
One Test Site
JESD 78, Class II
One Fabrication Site
ESD Protection Exceeds JESD 22
Extended Temperature Performance of –55 ° C
2000-V Human-Body Model (A114-A)
to 125 ° C
200-V Machine Model (A115-A)
Enhanced Diminishing Manufacturing
Sources (DMS) Support 1000-V Charged-Device Model (C101)
Enhanced Product-Change Notification
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
Qualification Pedigree
(1)
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
Available in the Texas Instruments
temperature cycle, autoclave or unbiased HAST,
NanoStar™ and NanoFree™ Packages
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
Supports 5-V V
CC
Operation
justifying use of this component beyond specified
Inputs Accept Voltages to 5.5 V
performance and environmental limits.
Max t
pd
of 4.1 ns at 3.3 V
Low Power Consumption, 10- µ A Max I
CC
± 24-mA Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce) <0.8 V
at V
CC
= 3.3 V, T
A
= 25 ° C
Typical V
OHV
(Output V
OH
Undershoot) >2 V at
V
CC
= 3.3 V, T
A
= 25 ° C
This dual inverter is designed for 1.65-V to 5.5-V V
CC
operation. The SN74LVC2G04 performs the Boolean
function Y = A.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

SN74LVC2G04MDCKREP 数据手册

TI(德州仪器)
13 页 / 0.72 MByte
TI(德州仪器)
4 页 / 0.34 MByte

SN74LVC2G04 数据手册

TI(德州仪器)
双反向器
TI(德州仪器)
TEXAS INSTRUMENTS  SN74LVC2G04DBVR.  芯片, 双路非门, SOT-23-6, 整卷
TI(德州仪器)
TEXAS INSTRUMENTS  SN74LVC2G04DCKR  非门, LVC系列, 1输入, 32 mA, 1.65V至5.5V, SC-70-6
TI(德州仪器)
TEXAS INSTRUMENTS  SN74LVC2G04DCKT  非门, LVC系列, 1输入, 32 mA, 1.65V至5.5V, SC-70-6
TI(德州仪器)
双非门 DUAL INVERTER GATE
TI(德州仪器)
IC 反相器 SN74LVC2G04YZPR 8-DSBGA/8-WCSP marking/标记 38NCC7
TI(德州仪器)
74LVC2G 系列,Texas Instruments### 74LVC 系列
TI(德州仪器)
TEXAS INSTRUMENTS  SN74LVC2G04MDCKREP  非门, LVC系列, 1输入, 1.65V至5.5V, SC-70-6
TI(德州仪器)
双非门 DUAL INVERTER GATE
TI(德州仪器)
双非门 DUAL INVERTER GATE
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