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SN8P26042AKG 数据手册 - Sonix（松翰）
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SN8P26042AKG数据手册
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SN8P2604A
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 48 Version 0.3
4
4
4
SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is
generated from the external oscillator circuit. The low-speed clock is generated from on-chip low-speed RC oscillator
circuit (ILRC 16KHz @3V, 32KHz @5V).
Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is
divided by 4 to be the instruction cycle (Fcpu).
) Normal Mode (High Clock): Fcpu = Fhosc / N, N = 1 ~ 8, Select N by Fcpu code option.
) Slow Mode (Low Clock): Fcpu = Flosc/4.
SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise
outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable.
4.2 CLOCK BLOCK DIAGRAM
Fhosc.
Fcpu = Fhosc/1 ~ Fhosc/8, Noise Filter Disable.
Fcpu = Fhosc/4 ~ Fhosc/8, Noise Filter Enable.
Flosc. Fcpu = Flosc/4
CPUM[1:0]
XIN
XOUT
STPHX HOSC
Fcpu Code Option
Fosc
Fosc
CLKMD
Fcpu
z HOSC: High_Clk code option.
z Fhosc: External high-speed clock.
z Flosc: Internal low-speed RC clock (about 16KHz@3V, 32KHz@5V).
z Fosc: System clock source.
z Fcpu: Instruction cycle.
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