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SST25VF512A-33-4C-SAE 数据手册 - Silicon Storage Tech
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SST25VF512A-33-4C-SAE数据手册
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Data Sheet
512 Kbit SPI Serial Flash
SST25VF512A
3
©2006 Silicon Storage Technology, Inc. S71264-02-000 1/06
PIN DESCRIPTION
FIGURE 1: PIN ASSIGNMENTS
TABLE 1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI Serial Data
Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data
Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device.
V
DD
Power Supply To provide power supply (2.7-3.6V).
V
SS
Ground
T1.0 1264
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
V
DD
HOLD#
SCK
SI
Top View
1264 08-soic P1.0
8-LEAD SOIC 8-CONTACT WSON
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
Top View
V
DD
HOLD#
SCK
SI
1264 08-wson P2.0
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