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STM32F479IGH6 数据手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
封装:
UFBGA-176
描述:
ARM Cortex-M4 180MHz 闪存：1MB RAM：384KB
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STM32F479IGH6数据手册
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Contents STM32F469xx and STM32F479xx
2/34 DocID028202 Rev 5
Contents
1 ARM
®
32-bit Cortex
®
-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . 6
1.1 Cortex®-M4 interrupted loads to stack pointer can cause
erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Summary of silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.1.1 Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . 11
2.1.2 Debugging Sleep/Stop mode with WFE/WFI entry . . . . . . . . . . . . . . . . 11
2.1.3 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 11
2.1.4 MPU attribute to RTC and IWDG registers could be managed
incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.5 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 12
2.1.6 Internal noise impacting the ADC accuracy . . . . . . . . . . . . . . . . . . . . . . 12
2.1.7 Wakeup from Standby mode with RTC . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.8 Data Cache might be corrupted during Flash Read While Write
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.9 FMC_SDNWEN alternate function on PA7 . . . . . . . . . . . . . . . . . . . . . . 14
2.2 RTC limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Spurious tamper detection when disabling the tamper channel . . . . . . . 14
2.2.2 Detection of a tamper event occurring before enabling the tamper
detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 14
2.3 IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 RVU and PVU flags are not reset in STOP mode . . . . . . . . . . . . . . . . . 15
2.4 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.2 Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . . 15
2.4.3 Mismatch on the “Setup time for a repeated Start condition” timing
parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.4 Data valid time (t
VD;DAT
) violated without the OVR flag being set . . . . . 16
2.4.5 Both SDA and SCL maximum rise time (t
r
) violated when VDD_I2C
bus is higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.6 Spurious Bus Error detection in master mode . . . . . . . . . . . . . . . . . . . . 17
2.5 SPI peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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