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STM8S207R8T6TR 数据手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
微控制器
封装:
LQFP-64
描述:
性能线， 24兆赫STM8S 8位MCU ，高达128 KB闪存，集成的EEPROM ， 10位ADC ，定时器， 2个UART ， SPI ， I²C ， CAN Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
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引脚图在P23P24P25P26P27P28P29P30P31P32P33Hot
典型应用电路图在P84P87
原理图在P12
封装尺寸在P23P92
型号编码规则在P112
封装信息在P91P92P93P94P95P96P97P98P99P100P101P102
功能描述在P13P14P15P16P17P18P19P20P21P22
技术参数、封装参数在P54P89
电气规格在P52P53P54P55P56P57P58P59P60P61P62P63
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STM8S207R8T6TR数据手册
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Pinouts and pin description STM8S207xx STM8S208xx
32/117 DocID14733 Rev 13
5.2 Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
69 55 39 35 - PE1/I
2
C_SCL I/O X XO1T
(3)
Port E1 I
2
C clock
70 56 40 36 - PE0/CLK_CCO I/O X XXHSO3XXPort E0
Configurable
clock output
71----PI6 I/OX XO1XXPort I6
72----PI7 I/OX
XO1XXPort I7
73 57 41 37 25 PD0/TIM3_CH2 I/O X
XXHSO3XXPort D0
Timer 3 -
channel 2
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
74 58 42 38 26 PD1/SWIM
(4)
I/O X X XHSO4XXPort D1
SWIM data
interface
75 59 43 39 27 PD2/TIM3_CH1 I/O X
XXHSO3XXPort D2
Timer 3 -
channel 1
TIM2_CH3
[AFR1]
76 60 44 40 28 PD3/TIM2_CH2 I/O X
XXHSO3XXPort D3
Timer 2 -
channel 2
ADC_ETR
[AFR0]
77 61 45 41 29
PD4/TIM2_CH1/B
EEP
I/O X
XXHSO3XXPort D4
Timer 2 -
channel 1
BEEP output
[AFR7]
78 62 46 42 30 PD5/ UART3_TX I/O X
XX O1XXPort D5
UART3 data
transmit
79 63 47 43 31
PD6/
UART3_RX
(1)
I/O X XX O1XXPort D6
UART3 data
receive
80 64 48 44 32 PD7/TLI I/O X
XX O1XXPort D7
Top level
interrupt
TIM1_CH4
[AFR4]
(5)
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as part
of the bootloader activation process and returned to the floating state before a return from the bootloader.
2. The beCAN interface is available on STM8S208xx devices only
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V
DD
are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
5. Available in 44-pin package only. On other packages, the AFR4 bit is reserved and must be kept at 0.
Table 6. Pin description (continued)
Pin number
Pin name
Type
Input Output
Main function
(after reset)
Default
alternate
function
Alternate
function
after remap
[option bit]
LQFP80
LQFP64
LQFP48
LQFP44
LQFP32
floating
wpu
Ext. interrupt
High sink
Speed
OD
PP
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