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TLC5947RHBTG4
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TLC5947RHBTG4数据手册
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GND
BLANK
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
SCLK
SIN
VCC
IREF
XLAT
SOUT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
1
2
6
8
10
12
13
15
16
3
4
5
7
9
11
14
32
31
27
25
23
21
20
18
17
30
29
28
26
24
22
19
GND
VCC
Thermal
Pad
GND
Via to
Heatsink
Layer
SIN
XLAT
SCLK
BLANK
TLC5947
SBVS114B JULY 2008REVISED JANUARY 2015
www.ti.com
10 Power Supply Recommendations
The VCC power supply voltage should be decoupled by placing a 0.1-µF ceramic capacitor close to the VCC pin
and GND plane. Depending on the panel size, several electrolytic capacitors must be placed on the board
equally distributed to get a well regulated LED supply voltage (V
LED
). The V
LED
voltage ripple must be less than
5% of its nominal value. Furthermore, the V
LED
must be set to the voltage calculated by Equation 3:
V
LED
> V
F
+ 0.4 V (10-mA constant-current example)
where
V
F
= maximum forward voltage of all LEDs. (3)
11 Layout
11.1 Layout Guidelines
Place the decoupling capacitor near the VCC pin and GND plane.
Place the current programming resistor R
IREF
close to the IREF pin and the IREFGND pin.
Route the GND pattern as widely as possible for large GND currents.
The routing wire between the LED cathode side and the device OUTXn pin must be as short and straight as
possible to reduce wire inductance.
When several ICs are chained, symmetric placements are recommended.
11.2 Layout Example
Figure 26. Layout Schematic
20 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: TLC5947

TLC5947RHBTG4 数据手册

TI(德州仪器)
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TLC5947 数据手册

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